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p reliminary W83193R-02/-04/-04a 83.3 mhz 3-dimm clock publication release date: april 1999 - 1 - revision a1 1.0 general description the W83193R-02/-04/-04a is a main board clock synthesizer which provides all clocks required for high-speed risc or cisc microprocessor such as intel pentiumpro, pentiumii, amd or cyrix. eight different frequency of cpu and pci clocks are externally selectable with smooth transitions. the W83193R-02/-04/-04a also provides i2c serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.5% or 1.5% center type spread spectrum. the W83193R-02/-04/-04a accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. high drive pci and sdram clock outputs typically provide greater than 1v / ns slew rate into 30 pf loads. cpu clock outputs typically provide better than 1v /ns slew rate into 20 pf loads as maintaining 50 5% duty cycle. the fixed frequency outputs as ref, 24 mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2.0 features supports pentium ? , pentium ? pro, pentium ? ii, amd and cyrix cpus with i 2 c. 4 cpu clocks 12 sdram clocks for 3 dims. 7 pci synchronous clocks. one ioapic clock for multiprocessor support. optional single or mixed supply: (v dd = v dd q3 = v dd q2 = v dd q2b = 3.3v) or (v dd = v dd q3 = 3.3v, v dd q2 = v dd 2b = 2.5v) < 250 ps skew among cpu and sdra m clocks. < 250 ps skew among pci clocks. smooth frequency switch with selections from 50 mhz to 83.3 mhz cpu. (w83193r-04) smooth frequency switch with selections from 50 mhz to 112 mhz cpu. (w83193r-04a) i 2 c 2-wire serial interface and i 2 c read back. spread spectrum function to reduce emi. programmable registers to enable/stop each output and select modes (mode as tri-state or normal) mode pin for power management 48 mhz for usb 24 mhz for super i/o packaged in 48-pin ssop
p reliminary W83193R-02/-04/-04a - 2 - 4.0 pin configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vdd ref0/cpu3.3#_2.5 vss xin xout vddq3 pciclk_f/*fs1 pciclk0/*fs2 vss pciclk1 pciclk2 pciclk3 pciclk4 vddq3 pciclk5/pci_stop# vss sdram11 sdram10 vddq3 sdram 9 sdram 8 vss sdata sdclk vddq2 ioapic ref1/cpu_stop# vss cpuclk0 cpuclk1 vddq2b cpuclk2 cpuclk3 vss sdram 0 sdram 1 sdram 2 vddq3 sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vss vddq3 48mhz/*fs0 24mhz/*mode 3.0 block diagram pll2 xtal osc spread spectrum pll1 latch por stop 1/2 control logic config. reg. stop pci clock divider ~ ~ 6 5 2 12 6 48 mhz 24 mhz ioapic ref(0:1) cpuclk(0:3) sdram(0:11) pciclk(0:5) pciclk_f xin xout fs(0:2)* 3 mode* cpu_stop# pci_stop# sdata sclk 4 cpu3.3#_2.5*
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 3 - revision a1 5.0 pin description in - input out - output i/o - bi-directional pin # - active low * - internal 250k w pull-up 5.1 crystal i/o symbol pin i/o function xin 4 in crystal input with internal loading capacitors and feedback resistors. xout 5 out crystal output at 14.318 mhz nominally. 5.2 cpu, sdram, pci clock outputs symbol pin i/o function cpuclk [ 0:3 ] 40, 41, 43, 44 out low skew (< 250 ps) clock outputs for host frequencies such as cpu, chipset and cache. v dd q2 is the supply voltage for these outputs. ioapic 47 out high drive buffered output of the crystal, and is powered by v dd q2. sdram [ 0:11] 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 o sdram clock outputs which have the same frequency as cpu clocks. pciclk_f/ *fs1 7 i/o latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. free running pci clock during normal operation. pciclk 0 / *fs2 8 i/o latched input for fs2 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. pci clock during normal operation. pciclk [ 1:4 ] 10, 11, 12, 13 out low skew (< 250 ps) pci clock outputs. pciclk5/ pci_stop# 15 i/o internal 250 k w pull-up. if mode = 1 (default), then this pin is a pci5 clock output. if mode = 0 , then this pin is pci_stop # and used in power management mode for synchronously stopping the all pci clocks.
p reliminary W83193R-02/-04/-04a - 4 - 5.3 i 2 c control interface symbol pin i/o function sdata 23 i/o serial data of i 2 c 2-wire control interface sdclk 24 in serial clock of i 2 c 2-wire control interface 5.4 fixed frequency outputs symbol pin i/o function ref0/cpu3.3#_2.5 2 i/o internal 250k w pull-up. latched input for cpu3.3#_2.5 at initial power up. reference clock during normal operation. latched high - v dd q2 = v dd q2b = 2.5v latched low - v dd q2 = v dd q2b = 3.3v ref1/cpu_stop# 46 i/o internal 250 k w pull-up. if mode = 1 (default), then this pin is a ref1 buffered output of the crystal. if mode = 0 , then this pin is cpu_stop# input used in power management mode for synchronously stopping the all cpu clocks. 24mhz / *mode 25 i/o internal 250 k w pull-up. latched input for mode at initial power up. 24 mhz output for super i/o during normal operation. 48mhz / *fs0 26 i/o internal 250 k w pull-up. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 48 mhz output for usb during normal operation. 5.5 power pins symbol pin function v dd 1 power supply for ref [0:1] crystal and core logic. v dd q2 42 power supply for cpuclk[0:3], either 2.5v or 3.3v. v dd q2b 48 power supply for ioapic output, either 2.5v or 3.3v. v dd q3 6, 14, 19, 30, 36 power supply for sdram, pciclk and 48/24 mhz outputs. v ss 3, 9, 16, 22, 27, 33, 39, 45 circuit ground.
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 5 - revision a1 6.0 frequency selection W83193R-02/-04 frequency table fs2 fs1 fs0 cpu, sdram (mhz) pci (mhz) ref, ioapic (mhz) 0 0 0 50 25 14.318 0 0 1 75 32 14.318 0 1 0 83.3 41.65 14.318 0 1 1 68.5 34.25 14.318 1 0 0 83.3 33.3 14.318 1 0 1 75 37.5 14.318 1 1 0 60 30 14.318 1 1 1 66.8 33.4 14.318 w83193r-04a frequency table fs2 fs1 fs0 cpu, sdram (mhz) pci (mhz) ref, ioapic (mhz) 0 0 0 50 25 14.318 0 0 1 100 50 14.318 0 1 0 83.3 41.65 14.318 0 1 1 68.5 34.25 14.318 1 0 0 90 45 14.318 1 0 1 75 37.5 14.318 1 1 0 112 56 14.318 1 1 1 66.8 33.4 14.318 7.0 cpu 3.3#_2.5 buffer selection cpu 3.3#_2.5 (pin 2) input level cpu & ioapic operate at 1 v dd = 2.5v 0 v dd = 3.3v 8.0 functional description 8.1 power management functions all clocks can be individually enabled or disabled via the 2-wire control interface. on power up, external circuitry should allow 3 ms for the vco to stabilize prior to enabling clock outputs to assure correct pulse widths. when mode = 0, pins 15 and 46 are inputs (pci_stop#), (cpu_stop#), when mode = 1, these functions are not available. a particular clock could be enabled as both the 2- wire serial control interface and one of these pins indicate that it should be enable.
p reliminary W83193R-02/-04/-04a - 6 - the W83193R-02/-04/-04a may be disabled in the low state according to the following table in order to reduce power consumption. all clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. the cpu and pci clocks transform between running and stop by waiting for one positive edge on pciclk_f followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. cpu_stop# pci_stop# cpu pci other clks xtal & vcos 0 0 low low running running 0 1 low running running running 1 0 running low running running 1 1 running running running running 8.2 2-wire i 2 c control interface the clock generator is a slave i 2 c component which can be read back the data stored in the latches for verification. all proceeding bytes must be sent to change one of the control bytes. the 2-wire control interface allows each clock output individually enabled or disabled. on power up, the W83193R-02/-04/-04a initializes with default register settings, and then it's optional to use the 2-wire control interface. the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high during normal data transfer. there are only two exceptions. one is a high-to-low transition on sdata while sdclk is high used to indicate the beginning of a data transfer cycle. the other is a low-to- high transition on sdata while sdclk is high used to indicate the end of a data transfer cycle. data is always sent as complete 8-bit bytes followed by an acknowledge generated. byte writing starts with a start condition followed by 7-bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. after successful reception of each byte, an acknowledge (low) on the sdata wire will be generated by the clock chip. controller can start to write to internal i 2 c registers after the string of data. the sequence order is as follows: bytes sequence order for i 2 c controller: clock address a(6:0) & r/w ack 8 bits dummy command code ack 8 bits dummy byte count ack byte0,1,2... until stop set r/w to 1 when read back, the data sequence is as follows: clock address a(6:0) & r/w ack byte 0 ack ack byte2, 3, 4... until stop byte 1 8.3 serial control registers the pin column lists the affected pin number and the @powerup column gives the state at true power up. registers are set to the values shown only on true power up. "command code" byte and "byte count" byte must be sent following the acknowledge of the address byte. although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the below described sequence (register 0, register 1, register 2, ....) will be valid and acknowledged.
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 7 - revision a1 8.3.1 register 0: cpu frequency select register (1 = enable, 0 = stopped) bit @powerup pin description 7 0 - 0 = 1.5% spread spectrum modulation 1 = 0.5% spread spectrum modulation 6 0 - ssel2 (frequency table selection by software via i 2 c) 5 0 - ssel1 (frequency table selection by software via i 2 c) 4 0 - ssel0 (frequency table selection by software via i 2 c) 3 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit 6:4 2 0 - 0 = spread spectrum center spread type 1 = spread spectrum down spread type 1 0 - 0 = normal 1 = spread spectrum enabled 0 0 - 0 = running 1 = tristate all outputs frequency table selection by software via i 2 c ssel2 ssel1 ssel0 cpu, sdram (mhz) pci (mhz) ref, ioapic (mhz) 0 0 0 50 25 14.318 0 0 1 75 32 14.318 0 1 0 83.3 41.65 14.318 0 1 1 68.5 34.25 14.318 1 0 0 83.3 33.3 14.318 1 0 1 75 37.5 14.318 1 1 0 60 30 14.318 1 1 1 66.8 33.4 14.318 function table function outputs description cpu pci sdram ref ioapic tri-state hi-z hi-z hi-z hi-z hi-z normal see table see table cpu 14.318 14.318
p reliminary W83193R-02/-04/-04a - 8 - 8.3.2 register 1: cpu, 48/24 mhz clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 1 - reserved 6 1 - reserved 5 1 - reserved 4 1 - reserved 3 1 40 cpuclk3 (active/ inactive) 2 1 41 cpuclk2 (active/ inactive) 1 1 43 cpuclk1 (active/ inactive) 0 1 44 cpuclk0 (active/ inactive) 8.3.3 register 2: pci clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 x - reserved 6 1 7 pciclk_f (active/ inactive) 5 1 15 pciclk5 (active/ inactive) 4 1 13 pciclk4 (active/ inactive) 3 1 12 pciclk3 (active/ inactive) 2 1 11 pciclk2 (active/ inactive) 1 1 10 pciclk1 (active/ inactive) 0 1 8 pciclk0 (active/ inactive) 8.3.4 register 3: sdram clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 1 28 sdram7 (active/ inactive) 6 1 29 sdram6 (active/ inactive) 5 1 31 sdram5 (active/ inactive) 4 1 32 sdram4 (active/ inactive) 3 1 34 sdram3 (active/ inactive) 2 1 35 sdram2 (active/ inactive) 1 1 37 sdram1 (active/ inactive) 0 1 38 sdram0 (active/ inactive)
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 9 - revision a1 8.3.5 register 4: additional sdram clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 x - reserved 6 x - reserved 5 x - reserved 4 x - reserved 3 1 17 sdram11 (active/ inactive) 2 1 18 sdram10 (active/ inactive) 1 1 20 sdram9 (active/ inactive) 0 1 21 sdram8 (active/ inactive) 8.3.6 register 5: peripheral control (1 = enable, 0 = stopped) bit @powerup pin description 7 x - reserved 6 x - reserved 5 x - reserved 4 1 47 ioapic (active/ inactive) 3 x - reserved 2 x - reserved 1 1 46 ref1 (active/ inactive) 0 1 2 ref0 (active/ inactive) 8.3.7 register 6: reserved register bit @powerup pin description 7 x - reserved 6 x - reserved 5 x - reserved 4 x - reserved 3 x - reserved 2 x - reserved 1 x - reserved 0 x - reserved
p reliminary W83193R-02/-04/-04a - 10 - 9.0 specifications 9.1 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. maximum conditions for extended periods may affect reliability. unused inputs must always be tied to an appropriate logic voltage level (ground or v dd ). parameter symbol rating voltage on any pin with respect to gnd v dd , v in -0.5v to +7.0v storage temperature t stg -65 c to +150 c ambient temperature t b -55 c to +125 c operating temperature t a 0 c to +70 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 9.2 ac characteristics v dd = v dd q3 = 3.3v 5%, v dd q2 = v dd q2b = 2.375v~2.9v , t a = 0 c to +70 c parameter sym. min. typ. max. units test conditions output duty cycle 45 50 55 % measured at 1.5v cpu/sdram to pci offset t off 1 4 ns 15 pf load measured at 1.5v skew (cpu-cpu), (pci- pci), (sdram-sdram) t skew 250 ps 15 pf load measured at 1.5v cpu/sdram cycle to cycle jitter t ccj 250 ps cpu/sdram absolute jitter t ja 500 ps jitter spectrum 20 db bandwidth from center bw j 500 khz output rise (0.4v - 2.0v) & fall (2.0v - 0.4v) time t tlh t thl 0.4 1.6 ns 15 pf load on cpu and pci outputs overshoot/undershoot beyond power rails v over 0.7 1.5 v 22 w at source of 8 inch pcb run to 15 pf load ring back exclusion v rbe 0.7 2.1 v ring back must not enter this range.
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 11 - revision a1 9.3 dc characteristics v dd = v dd q3 = 3.3v 5%, v dd q2 = v dd q2b = 2.375v~2.9v , t a = 0 c to +70 c parameter sym. min. typ. max. units test conditions input low voltage v il 0.8 vdc input high voltage v ih 2.0 vdc input low current i il -66 m a input high current i ih 5 m a output low voltage i ol = 4 ma v ol 0.4 vdc all outputs output high voltage i oh = 4 ma v oh 2.4 vdc all outputs using 3.3v power tri-state leakage current i oz 10 m a dynamic supply current for v dd + v dd q3 i dd3 ma cpu = 66.6 mhz pci = 33.3 mhz with load dynamic supply current for v dd q2 + v dd q2b i dd2 ma same as above cpu stop current for v dd + v dd q3 i cpus3 ma same as above cpu stop current for v dd q2 + v dd q2b i cpus2 ma same as above pci stop current for v dd + v dd q3 i pd3 ma 9.4 buffer characteristics 9.4.1 type 1 buffer for cpu (0:3) parameter symbol min. typ. max. units test conditions pull-up current min. i oh (min.) -27 ma vout = 1.0v pull-up current max. i oh (max.) -27 ma vout = 2.0v pull-down current min. i ol (min.) tbd ma vout = 1.2v pull-down current max. i ol (max.) 27 ma vout = 0.3v rise/fall time min. between 0.4v and 2.0v t rf (min.) 0.4 ns 10 pf load rise/fall time max. between 0.4v and 2.0v t rf (max.) 1.6 ns 20 pf load
p reliminary W83193R-02/-04/-04a - 12 - 9.4.2 type 2 buffer for ioapic parameter symbol min. typ. max. units test conditions pull-up current min. i oh (min.) ma vout = 1.4v pull-up current max. i oh (max.) -29 ma vout = 2.7v pull-down current min. i ol (min.) ma vout = 1.0v pull-down current max. i ol (max.) 28 ma vout = 0.2v rise/fall time min. between 0.7v and 1.7v t rf (min.) 0.4 ns 10 pf load rise/fall time max. between 0.7v and 1.7v t rf (max.) 1.8 ns 20 pf load 9.4.3 type 3 buffer for ref1, 24 mhz, 48 mhz parameter symbol min. typ. max. units test conditions pull-up current min. i oh (min.) -29 ma vout = 1.0v pull-up current max. i oh (max.) -23 ma vout = 3.135v pull-down current min. i ol (min.) 29 ma vout = 1.95v pull-down current max. i ol (max.) ma vout = 0.4v rise/fall time min. between 0.8v and 2.0v t rf (min.) 1.0 ns 10 pf load rise/fall time max. between 0.8v and 2.0v t rf (max.) 4.0 ns 20 pf load 9.4.4 type 4 buffer for ref0 and sdram (0:11) parameter symbol min. typ. max. units test conditions pull-up current min. i oh (min.) ma vout = 1.65v pull-up current max. i oh (max.) -46 ma vout = 3.135v pull-down current min. i ol (min.) ma vout = 1.65v pull-down current max. i ol (max.) 53 ma vout = 0.4v rise/fall time min. between 0.8v and 2.0v t rf (min.) 0.5 ns 20 pf load rise/fall time max. between 0.8v and 2.0v t rf (max.) 1.3 ns 30 pf load
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 13 - revision a1 9.4.5 type 5 buffer for pciclk (0:5, f) parameter symbol min. typ. max. units test conditions pull-up current min. i oh (min.) -33 ma vout = 1.0v pull-up current max. i oh (max.) -33 ma vout = 3.135v pull-down current min. i ol (min.) 30 ma vout = 1.95v pull-down current max. i ol (max.) 38 ma vout = 0.4v rise/fall time min. between 0.8v and 2.0v t rf (min.) 0.5 ns 15 pf load rise/fall time max. between 0.8v and 2.0v t rf (max.) 2.0 ns 30 pf load 10.0 power management timing 10.1 cpu_stop# timing diagram (synchronous) cpuclk (internal) pciclk (internal) pciclk_f cpu_stop# cpuclk[0:3] sdram 1 2 1 2 for synchronous chipset, cpu_stop# pin is a synchronous "active low" input pin used to stop the cpu clocks for low power operation. this pin is asserted synchronously by the external control logic at the rising edge of free running pci clock(pciclk_f). all other clocks will continue to run while the cpu clocks are stopped. the cpu clocks will always be stopped in a low state and resume output with full pulse width. in this case, cpu "clocks on latency" is less than 2 cpu clocks and "clocks off latency" is less then 2 cpu clocks.
p reliminary W83193R-02/-04/-04a - 14 - 10.2 pci_stop# timing diagram (synchronous) cpuclk (internal) pciclk (internal) pciclk_f pci_stop# pciclk[0:5] 1 2 1 2 for synchronous chipset, pci_stop# pin is a synchronous active low ? input pin used to stop the pciclk [0:5] for low power operation. this pin is asserted synchronously by the external control logic at the rising edge of free running pci clock(pciclk_f). all other clocks will continue to run while the pci clocks are stopped. the pci clocks will always be stopped in a low state and resume output with full pulse width. in this case, pci clocks on latency ? is less than 1 pci clocks and clocks off latency ? is less then 1 pci clocks. 11.0 operation of dual fuction pins pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this device (see pin description). during power up, these pins are in input mode (see figure 1), therefore, and are considered input select pins. when v dd reaches 2.5v, the logic level that is present on these pins are latched into their appropriate internal registers. once the correct information are properly latched, these pins will change into output pins and will be pulled low by default. at the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency. within 3ms input output output tri-state output pull-low 2.5v output tri-state output pull-low #2 ref0/cpu3.3#_2.5 #7 pciclk_f/fs1 #8 pciclk0/fs2 #25 24/mode #26 48/fs0 all other clocks vdd each of these pins are a large pull-up resistor (250 k w @3.3v) inside. the default state will be logic 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. under these conditions, an external 10 k w resistor is recommended to be
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 15 - revision a1 connected to v dd if logic 1 is expected. otherwise, the direct connection to ground if a logic 0 is desired. the 10 k w resistor should be place before the serious terminating resistor. note that these logic will only be latched at initial power on. if optional emi reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. these capacitor has typical values ranging from 4.7 pf to 22 pf. device pin v ground ground 10 k series terminating resistor clock trace emi reducing cap 10 k w w optional dd device pin v pad ground pad programming header series terminating resistor clock trace emi reducin gcap ground 10 k w optional dd
p reliminary W83193R-02/-04/-04a - 16 - 12.0 power supply suggestion 1. a solid ground plane should be placed around the clock device. ground connections should be tied to this main ground plane as short as possible. no cuts should be made in the ground plane around the device. 2. c21,c22,c31,c36 are decoupling capacitors ( 0.1 m f surface mount, low esr, ceramic capacitors.) they should be placed as possibl e as the v dd pin and the ground via. 3. c1 and c2 are supply filtering capacitors for low frequency power supply noise. a 22 m f (or 10 m f) tantalum capacitor is recommended. 4. use of ferrite bead (fb) are recommended to further reduce the power supply noise. 5. the power supply race to the v dd pins must be thick enough so that voltage drops across the trace resistance is negligible. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v 2 plane fb2 v 2 (3.3v or 2.5v) c2 c21 c22 c36 c35 c34 c33 c32 c31 fb1 v plane c1 v (3.3v) dd dd dd dd
p reliminary W83193R-02/-04/-04a publication release date: april 1999 - 17 - revision a1 13.0 ordering information part number package type production flow W83193R-02/-04 48-pin ssop commercial, 0 c to +70 c 14.0 how to read the top marking w 8 3 1 9 3 r - 0 2 2 8 0 5 1 2 3 4 8 1 4 g b b 1st line: winbond logo and the type number: W83193R-02/-04 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 814 g b b 814 : packages made in ' 98 , week 14 g : assembly house id; a means ase, s means spil, g means gr bb : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
p reliminary W83193R-02/-04/-04a - 18 - 15.0 package dimensions headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792646 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice. please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.

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